Electronic chips, such as semiconductor chips, have evolved continuously towards higher functionality and integration. As a consequence, the number of input/output (I/O) interconnects of packages for such chips have increased. Electronics packages have evolved from dual in-line packages (DIPs) with I/Os along two edges of the package and quad flat packages (QFPs) with I/Os along all four edges of the package to ball grid arrays (BGAs) with I/Os at the whole bottom surface, in order to arrange more I/Os with acceptable pitch (or distance between neighboring I/Os).
A next step in packaging technology is the so called 3D (3 Dimensional) packaging technique, where I/Os are on both the top and the bottom surfaces of the package, such that components can be stacked on top of each other on a printed circuit board (PCB), thereby saving space compared with e.g. components mounted side by side on a PCB. For example, US 2007/0296065 A1 discloses a 3-dimensional electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit.
Although the 3D packaging technology described above provides an improved utilization of space e.g. compared with electronic devices mounted side by side on a PCB, it is desirable to provide electronic packaging technology with even further improved utilization of space.